hsms-281x surface?mount ?rf? schottky?barrier? diodes data sheet description/applications these schottky diodes are specifcally designed for both analog and digital applications. this series ofers a wide range of specifc a tions and package co nfgur a tions to give the designer wide fex i bility. the hsms?281x series of diodes features very low ficker (1/f ) noise. note that avagos manufacturing techniques assure that dice found in pairs and quads are taken from adjacent sites on the wafer, assuring the highest degree of match. package lead code identifcation, sot-23/sot-143 (top view) common cathode #4 unconnected pai r #5 common anode #3 series #2 single #0 1 2 3 1 2 3 4 ring quad #7 1 2 3 4 bridge quad #8 1 2 3 4 1 2 3 1 2 3 1 2 3 package lead code identifcation, sot-323 (top view) package lead code identifcation, sot-363 (top view) common cathode f common anode e series c single b common cathode quad m unconnected trio l bridge quad p common anode quad n ring quad r 1 2 3 6 5 4 high isolation unconnected pair k 1 2 3 6 5 4 1 2 3 6 5 4 1 2 3 6 5 4 1 2 3 6 5 4 1 2 3 6 5 4 notes: 1. package marking provides orientation and identifcation. 2. see electrical specifcations for appropriate package marking. pin connections and package marking features ? surface mount packages ? low flicker noise ? low fit (failure in time) rate* ? six ? sigma quality level ? single, dual and quad versions ? tape and reel options available ? lead ? free ? for more information see the surface mount schottky reliability data sheet. gux 1 2 3 6 5 4
2 electrical specifcations t c = 25c, single diode [3] maximum maximum minimum maximum forward reverse typical part package breakdown forward voltage leakage maximum dynamic number marking lead voltage voltage v f (v) @ i r (na) @ capacitance resistance hsms [4] code code confguration v br (v) v f (mv) i f (ma) v r (v) c t (pf) r d (?) [5] 2810 b0 0 single 20 410 1.0 35 200 15 1.2 15 2812 b2 2 series 2813 b3 3 common anode 2814 b4 4 common cathode 2815 b5 5 unconnected pair 2817 b7 7 ring quad [4] 2818 b8 8 bridge quad [4] 281b b0 b single 281c b2 c series 281e b3 e common anode 281f b4 f common cathode 281k bk k high isolation unconnected pair 281l bl l unconnected trio test conditions i r = 10 m a i f = 1 ma v f = 0 v i f = 5 ma f = 1 mhz absolute maximum ratings [1] t c = 25c symbol parameter unit sot-23/sot-143 sot-323/sot-363 i f forward current (1 s pulse) amp 1 1 p iv peak inverse voltage v same as v br same as v br t j junction temperature c 150 150 t stg storage temperature c ? 65 to 150 ? 65 to 150 jc thermal resistance [2] c/w 500 150 notes: 1. operation in excess of any one of these conditions may result in permanent damage to the device. 2. t c = +25c, where t c is defned to be the temperature at the package pins where contact is made to the circuit board. esd warning: handling precautions should be taken to avoid static discharge. notes: 1. ? v f for diodes in pairs and quads in 15 mv maximum at 1 ma. 2. ? c to for diodes in pairs and quads is 0.2 pf maximum. 3. efective carrier lifetime ( ) for all these diodes is 100 ps maximum measured with krakauer method at 5 ma. 4. see section titled quad capacitance. 5. r d = r s + 5.2 f at 25c and i f = 5 ma.
3 quad capacitance capacitance of schottky diode quads is measured using an hp4271 lcr meter. this instrument efectively isolates individual diode branches from the others, allowing ac ? curate capacitance measurement of each branch or each diode. the conditions are: 20 mv r.m.s. voltage at 1 mhz. avago defnes this measurement as cm, and it is equiva ? lent to the capac i tance of the diode by itself. the equiva ? lent diagonal and adj a cent capaci? tances can then be cal ? culated by the formulas given below. in a quad, the diagonal capac i tance is the capacitance be ? tween points a and b as shown in the fgure below. the diagonal capacitance is calculated using the following formula c j r j r s r j = 8.33 x 10 -5 nt i b + i s where i b = e xter nally applied bias current in amps i s = saturation current (see tab le of spice parameters) t = temperature , k n = ideality f actor (see tab le of spice parameters) note: to eff ectiv ely model the pac kaged hsms-281x product, please ref er to application note an1124. r s = ser ies resistance (see ta b le of spice parameters) c j = junction capacitance (see ta b le of spice parameters) linear equivalent circuit model diode chip esd warning: handling precautions should be taken to avoid static discharge. spice parameters parameter units hsms-281x b v v 25 c j0 pf 1.1 e g ev 0.69 i bv a e?5 i s a 4.8e?9 n 1.08 r s f 10 p b v 0.65 p t 2 m 0.5 c 1 x c 2 c 3 x c 4 c diagona l = _______ + _______ c 1 + c 2 c 3 + c 4 1 c adjacen t = c 1 + ____________ 1 1 1 ?? + ?? + ?? c 2 c 3 c 4 r j = 8.33 x 10 -5 nt i b + i s c 1 x c 2 c 3 x c 4 c diagona l = _______ + _______ c 1 + c 2 c 3 + c 4 1 c adjacen t = c 1 + ____________ 1 1 1 ?? + ?? + ?? c 2 c 3 c 4 r j = 8.33 x 10 -5 nt i b + i s the equivalent adjacent capacitance is the capacitance between points a and c in the fgure below. this capaci ? tance is calculated using the following formula this information does not apply to cross ? over quad di ? odes.
4 typical performance, t c = 25c (unless otherwise noted), single diode figure 1. forward current vs. forward v oltage at te mperatures. 0 0.1 0.3 0.2 0.5 0.6 0.4 0.8 0.7 i f ? forward current (ma) v f ? forward voltage (v) 0.01 10 1 0.1 100 t a = +125c t a = +75c t a = +25c t a = ?25c figure 2. reverse current vs. reverse voltage at temperatures. 0 5 15 i r ? reverse current (na) v r ? reverse voltage (v) 10 1 1000 100 10 100,000 10,000 t a = +125c t a = +75c t a = +25c figure 3. dynamic resistance vs. forward current. 0.1 1 100 r d ? dynamic resistance () i f ? forward current (ma) 10 1 10 1000 100 figure 4. total capacitance vs. reverse voltage. 0 2 6 4 1 0 1 2 8 1 6 14 c t ? capacitance (pf) v r ? reverse voltage (v) 0 0.75 0.50 0.25 1.25 1 v f - forward voltage (v) figure 5. typical v f match, pairs and quads. 30 10 1 0.3 30 10 1 0.3 i f - forward current (ma) v f - forward voltage difference (mv) 0.2 0.4 0.6 0.8 1.0 1.2 1.4 i f (left scale) v f (right scale)
5 applications information introduction product selection avagos family of schottky products provides unique solu ? tions to many design problems. the frst step in choosing the right product is to select the diode type. all of the products in the hsms?282x fam ? ily use the same diode chip, and the same is true of the hsms ? 281x and hsms ? 280x families. each family has a dif ? ferent set of characteristics which can be compared most easily by consulting the spice parameters in table 1. a review of these data shows that the hsms ? 280x family has the highest breakdown voltage, but at the expense of a high value of series resistance (r s ). in applications which do not require high voltage the hsms ? 282x family, with a lower value of series resistance, will ofer higher current carrying capacity and better performance. the hsms ?281x family is a hybrid schottky (as is the hsms ? 280x), ofering lower 1/f or ficker noise than the hsms ? 282x family. in general, the hsms ? 282x family should be the designers frst choice, with the ? 280x family reserved for high volt ? age applications and the hsms ? 281x family for low ficker noise applications. assembly instructions sot-323 pcb footprint a recommended pcb pad layout for the miniature sot ? 323 (sc ? 70) package is shown in figure 6 (dimensions are in inches). this layout provides ample allowance for pack ? age placement by automated assembly equipment with ? out adding parasitics that could impair the performance. table 1. typical spice parameters. parameter units hsms-280x hsms-281x hsms-282x b v v 75 25 15 c j0 pf 1.6 1.1 0.7 e g ev 0.69 0.69 0.69 i bv a 1 e?5 1 e?5 1 e?4 i s a 3 e?8 4.8 e?9 2.2 e?8 n 1.08 1.08 1.08 r s ? 30 10 6.0 p b (v j ) v 0.65 0.65 0.65 p t (xti) 2 2 2 m 0.5 0.5 0.5 0.026 0.039 0.079 0.022 dimensions in inches 0.026 0.079 0.018 0.039 dimensions in inches figure 6. recommended pcb pad layout for avagos sc70 3l/sot - 323 products. assembly instructions sot-363 pcb footprint a recommended pcb pad layout for the miniature sot ? 363 (sc ? 70, 6 lead) package is shown in figure 7 (dimen ? sions are in inches). this layout provides ample allowance for package placement by automated assembly equip ? ment without adding parasitics that could impair the per ? formance. figure 7. recommended pcb pad layout for avagos sc70 6l/sot - 363 products.
6 figure 8. surface mount assembly profle. 2 5 t i m e t e m p e r a t u r e t p t l t p t l t 2 5 c t o p e a k r a m p - u p t s t s m i n r a m p - d o w n p r e h e a t c r i t i c a l z o n e t l t o t p t s m a x lead-free refow profle recommendation (ipc/jedec j-std-020c) refow parameter lead-free assembly average ramp ? up rate (liquidus temperature (t s(max) to peak) 3c/ second max preheat temperature min (t s(min) ) 150c temperature max (t s(max) ) 200c time (min to max) (t s ) 60? 180 seconds ts(max) to tl ramp ? up rate 3c/second max time maintained above: temperature (t l ) 217c time (t l ) 60? 150 seconds peak temperature (t p ) 260 +0/?5c time within 5 c of actual peak temperature (t p ) 20? 40 seconds ramp ? down rate 6c/second max time 25 c to peak temperature 8 minutes max note 1: all temperatures refer to topside of the package, measured on the package body surface smt assembly reliable assembly of surface mount components is a com ? plex process that involves many material, process, and equipment factors, including: method of heating (e.g., ir or vapor phase refow, wave soldering, etc.) circuit board material, conductor thickness and pattern, type of solder alloy, and the thermal conductivity and thermal mass of components. components with a low mass, such as the sot package, will reach solder refow temperatures faster than those with a greater mass. avagos sot diodes have been qualifed to the time ? tem ? perature profle shown in figure 8. this profle is repre ? sentative of an ir refow type of surface mount assembly process. after ramping up from room temperature, the circuit board with components attached to it (held in place with solder paste) passes through one or more preheat zones. the preheat zones increase the temperature of the board and components to prevent thermal shock and begin evaporating solvents from the solder paste. the refow zone briefy elevates the temperature sufciently to pro ? duce a refow of the solder. the rates of change of temperature for the ramp ? up and cool ? down zones are chosen to be low enough to not cause deformation of the board or damage to compo ? nents due to thermal shock. the maximum temperature in the refow zone (t max ) should not exceed 260c. these parameters are typical for a surface mount assem ? bly process for avago diodes. as a general guideline, the circuit board and components should be exposed only to the minimum temperatures and times necessary to achieve a uniform refow of solder.
7 package dimensions outline 23 (sot-23) outline sot-323 (sc-70 3 lead) part number ordering information no. of part number devices container hsms?281x?tr2g 10000 13" reel hsms?281x?tr1g 3000 7" reel hsms?281x?blkg 100 antistatic bag x = 0, 2, 3, 4, 5, 7, 8, b, c, e, f, k, l e b e 2 e 1 e 1 c e x x x l d a a 1 n o t e s : x x x - p a c k a g e m a r k i n g d r a w i n g s a r e n o t t o s c a l e d i m e n s i o n s ( m m ) m i n . 0 . 7 9 0 . 0 0 0 0 . 3 0 0 . 0 8 2 . 7 3 1 . 1 5 0 . 8 9 1 . 7 8 0 . 4 5 2 . 1 0 0 . 4 5 m a x . 1 . 2 0 0 . 1 0 0 0 . 5 4 0 . 2 0 3 . 1 3 1 . 5 0 1 . 0 2 2 . 0 4 0 . 6 0 2 . 7 0 0 . 6 9 s y m b o l a a 1 b c d e 1 e e 1 e 2 e l e b e 1 e 1 c e x x x l d a a 1 n o t e s : x x x - p a c k a g e m a r k i n g d r a w i n g s a r e n o t t o s c a l e d i m e n s i o n s ( m m ) m i n . 0 . 8 0 0 . 0 0 0 . 1 5 0 . 0 8 1 . 8 0 1 . 1 0 1 . 8 0 0 . 2 6 m a x . 1 . 0 0 0 . 1 0 0 . 4 0 0 . 2 5 2 . 2 5 1 . 4 0 2 . 4 0 0 . 4 6 s y m b o l a a 1 b c d e 1 e e 1 e l 1 . 3 0 t y p i c a l 0 . 6 5 t y p i c a l
8 device orientation for outline sot-143 note: "ab" represents package marking code. "c" re p resents date code. end vie w 8 mm 4 mm top view abc abc abc abc for outlines sot-23, -323 for outline sot-363 user feed direction cover tape carrier tape reel note: "ab" represents package marking code . "c" represents date code . end vi e w 8 mm 4 mm top view ab c a bc ab c a bc end vi e w 8 mm 4 mm top view note: "ab" represents package marking code . "c" represents date code . ab c ab c ab c ab c outline 143 (sot-143) outline sot-363 (sc-70 6 lead) e b e2 b1 e1 e1 c e xxx l d a a1 notes: xxx-package marking drawings are not to scale dimensions (mm) min. 0.79 0.013 0.36 0.76 0.086 2.80 1.20 0.89 1.78 0.45 2.10 0.45 max. 1.097 0.10 0.54 0.92 0.152 3.06 1.40 1.02 2.04 0.60 2.65 0.69 symbo l a a1 b b1 c d e1 e e1 e2 e l e h e d e a 1 b a a 2 d i m e n s i o n s ( m m ) m i n . 1 . 1 5 1 . 8 0 1 . 8 0 0 . 8 0 0 . 8 0 0 . 0 0 0 . 1 5 0 . 0 8 0 . 1 0 m a x . 1 . 3 5 2 . 2 5 2 . 4 0 1 . 1 0 1 . 0 0 0 . 1 0 0 . 3 0 0 . 2 5 0 . 4 6 s y m b o l e d h e a a 2 a 1 e b c l 0 . 6 5 0 b c s l c
9 tape dimensions and product orientation for outline sot-23 for outline sot-143 9 max a 0 p p 0 d p 2 e f w d 1 ko 8 max b 0 13. 5 max t1 description symbo l s ize (mm) size (inches) lengt h width depth pitch bottom hole diamete r a 0 b 0 k 0 p d 1 3.15 0.10 2.77 0.10 1.22 0.10 4.00 0.10 1.00 + 0. 05 0.124 0.004 0.109 0.004 0.048 0.004 0.157 0.004 0.039 0.002 cavity diameter pitch position d p 0 e 1.50 + 0.10 4.00 0.10 1.75 0.10 0.059 + 0.004 0.157 0.004 0.069 0.004 perforation width thickness w t1 8.00 + 0.30 ? 0.10 0.229 0.013 0.315 + 0.012 ? 0.004 0.009 0.0005 carrier tape cavity to perforation (width direction ) cavity to perforation (length direction ) f p 2 3.50 0.05 2.00 0.05 0.138 0.002 0.079 0.002 distance betwee n centerline w f e p 2 p 0 d p d 1 description symbo l s ize (mm) size (inches) lengt h widt h depth pitch bottom hole diameter a 0 b 0 k 0 p d 1 3.19 0.10 2.80 0.10 1.31 0.10 4.00 0.10 1.00 + 0. 25 0.126 0.00 4 0.110 0.00 4 0.052 0.00 4 0.157 0.00 4 0.039 + 0 .010 cavity diameter pitch position d p 0 e 1.50 + 0.10 4.00 0.10 1.75 0.10 0.059 + 0.00 4 0.15 7 0.004 0.06 9 0.004 perforation widt h thickness w t1 8.00 + 0.30 ? 0.10 0.254 0.013 0.315+ 0.012 ? 0.004 0.010 0 0.0005 carrier tape cavity to perforation (width direction ) cavity to perforation (length direction ) f p 2 3.50 0.05 2.00 0.05 0.138 0.00 2 0.079 0.00 2 distance a 0 9 9 x a m max t 1 b 0 k 0
tape dimensions and product orientation for outlines sot-323, -363 p p 0 p 2 f w c d 1 d e a 0 an t 1 (carrier tape thickness) t t (cover tape thickness ) an b 0 k 0 description symbo l s ize (mm) size (inches) length width dept h pitch bottom hole diameter a 0 b 0 k 0 p d 1 2.40 0.10 2.40 0.10 1.20 0.10 4.00 0.10 1.00 + 0.2 5 0.09 4 0.004 0.09 4 0.004 0.04 7 0.004 0.15 7 0.004 0.039 + 0.01 0 cavity diameter pitch position d p 0 e 1.55 0.05 4.00 0.10 1.75 0.10 0.06 1 0.002 0.15 7 0.004 0.06 9 0.004 perforation width thicknes s w t 1 8.00 0.30 0.25 4 0.02 0.31 5 0.012 0.0100 0.0008 carrier tape cavity to perforation (width direction) cavity to perforation (length direction) f p 2 3.50 0.05 2.00 0.05 0.13 8 0.002 0.07 9 0.002 distance for sot-323 (sc70-3 lead ) a n 8 c ma x for sot-363 (sc70-6 lead ) 1 0 c ma x angle width tape thicknes s c t t 5. 4 0.10 0.06 2 0.001 0.20 5 0.004 0.0025 0.00004 cover tape for ? product? information?and?a? complete?list?of? distributors,?please?go? to?our? web? site:????????? www.avagotech.com avago, ? avago? technologies, ?and?the?a?logo? are? trademarks?of? avago? technologies ?in?the? united? states?and?other? countries. data ? subject? to? change.?? copyright???2005-2009? avago? technologies. ? all? rights? reserved.?? obsoletes?5989-4021en av02-1367en ?-? may?29,?2009
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